View WED2ZL361MSJ-BC_2256875.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

white electronic designs

a ddress bus (sa 0 C sa 19 ) dqa, dqb dqpa, dqpb dqc, dqd dqpc, dqpd dqa C dqd dqpa C dqpd 1m x 18 1m x 18 clk cke adv lbo cs1 cs2 cs2 oe we zz clk cke adv lbo ce1 ce2 ce2 oe we zz clk cke adv lbo cs1 cs2 cs2 oe we zz bwd bwa bwc bwb v ddq sa sa sa sa sa v ddq nc ce2 sa adv sa ce2 nc
nc sa sa v dd sa sa nc dq c dqp c v ss nc v ss dqp b dq b dq c dq c v ss ce1 v ss dq b dq b v ddq dq c v ss oe v ss dq b v ddq dq c dq c bw c sa b w b dq b dq b dq c dq c v ss we v ss dq b dq b v ddq v dd nc v dd nc v dd v ddq dq d dq d v ss clk v ss dq a dq a dq d dq d bw d nc bw a dq a dq a v ddq dq d v ss cke v ss dq a v ddq dq d dq d v ss sa1 v ss dq a dq a dq d dqp d v ss sa0 v ss dqp a dq a nc sa lbo v dd nc sa nc nc nc sa sa sa sa zz v ddq nc nc nc nc nc v ddq
fast clock speed: 250, 225, 200, 166, 150, 133mhz fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns fast oe access times: 2.6, 2.8, 3.0, 3.5ns, 3.8ns, 4.2ns separate +2.5v 5% power supplies for core, i/o (vdd, vddq) snooze mode for reduced-standby power individual byte write control clock-controlled and registered addresses, data i/os and control signals burst control (interleaved or linear burst) packaging: ? 119-bump bga package jedec pin configuration low capacitive bus loading the wedc syncburst - sram family employs high-speed, low-power cmos designs that are fabricated using an advanced cmos process. wedc?s 36mb syncburst srams integrate two 1m x 18 srams into a single bga package to provide 1m x 36 configuration. all synchronous inputs pass through registers controlled by a positive-edge- triggered single-clock input (clk). the nbl or no bus latency memory utilizes all the bandwidth in any combi- nation of operating cycles. address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. burst order con- trol must be tied ?high or low.? asynchronous inputs include the sleep mode enable (zz). output enable controls the outputs at any given time. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. note: nbl (no bus latency) is equivalent to zbt?. ! "
##$% !&'

"
()*
white electronic designs write operation occurs when we is driven low at the rising edge of the clock. bw[d:a] can be used for byte write operation. the pipe-lined nbl ssram uses a late- late write cycle to utilize 100% of the bandwidth. at the first rising edge of the clock, we and address are regis- tered, and the data associated with that address is required two cycles later. subsequent addresses are generated by adv high for the burst access as shown below. the starting point of the burst sequence is provided by the external address. the burst address counter wraps around to its initial state upon completion. the burst sequence is determined by the state of the lbo pin. when this pin is low, linear burst sequence is selected. when this pin is high, interleaved burst sequence is selected. during normal operation, zz must be driven low. when zz is driven high, the sram will enter a power sleep mode after 2 cycles. at this time, internal state of the sram is preserved. when zz returns to low, the sram operates after 2 cycles of wake up time.
first address 0 0 011011 01101100 10110001 fourth address 1 1 000110

1. lbo pin must be tied to high or low, and floating state must not be allowed. 2. lbo cannot change after initial power up. !
first address 00011011 01001110 10110001 fourth address 11100100
the wed2zl361msj is an nbl ssram designed to sustain 100% bus bandwidth by eliminating turnaround cycles when there is transition from read to write, or vice versa. all inputs (with the exception of oe, lbo and zz) are synchronized to rising clock edges. all read, write and deselect cycles are initiated by the adv input. subsequent burst addresses can be inter- nally generated by the burst advance pin (adv). adv should be driven to low once the device has been deselected in order to load a new address for next operation. the clock enable (cke) pin allows the operation of the chip to be suspended as long as necessary. when cke is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. nbl ssram latches external address and initiates a cycle when cke and adv are driven low at the rising edge of the clock. output enable (oe) can be used to disable the output at any given time. read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, cke is driven low, the write enable input signals we are driven high, and adv driven low. the internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. at the second clock edge the data is driven out of the sram. during read operation oe must be driven low for the device to drive out the requested data.

white electronic designs "# $% &" &# " '" ' !!((! ) hlxxx l n/a deselect xhxxx l n/a continue deselect llhxll external address begin burst read cycle xhxx l l next address continue burst read cycle llhxhl external address nop/dummy read xhxxh l next address dummy read llllxl external address begin burst write cycle xhxlxl next address continue burst write cycle lllhxl n/a nop/write abort xhxhx l next address write abort xxxxxh current address ignore clock 1. x means ?don?t care.? 2. the rising edge of clock is symbolized by ( ) 3. a continue deselect cycle can only be entered if a deselect cycle is executed first. 4. write = l means write operation in write truth table. write = h means read operation in write truth table. 5. operation finally depends on status of asynchronous input pins (zz and oe). 6. cex refers to the combination of ce1, ce2 and ce2.

&" & &* &( &! ) hxxxx read l l h h h write byte a l h l h h write byte b l h h l h write byte c l h h h l write byte d lllll w rite all bytes l hhhh write abort/nop 1. x means ?don?t care.? 2. all inputs in this table must meet setup and hold time around the rising edge of clk ( ).

"
()*
white electronic designs

voltage on v dd supply relative to vss -0.3v to +3.6v vin (dqx) -0.3v to +3.6v vin (inputs) -0.3v to +3.6v storage temperature (bga) -55c to +125c short circuit output current 100ma

!
* stress greater than those listed under ?absolute maximum ratings: may cause permanent damage to the device. this is a stress r ating only and functional operation of the device at these or any other conditions greater than those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating condtions for extended periods may affect reliability . "#$%&'(&)* +,-). )*/&(&)*# &* 01 2*&(# 3)("# input high (logic 1) voltage v ih 1.7 v dd +0.3 v 1 input low (logic 0) voltage v il -0.3 0.7 v 1 input leakage current ili 0v v in v dd -5 5 a 2 output leakage current i lo output(s) disabled, 0v v in v dd -5 5 a output high voltage v oh i oh = -1.0ma 2.0 --- v 1 output low voltage v ol i ol = 1.0ma --- 0.4 v 1 supply voltage v dd 2.375 2.625 v 1 1. all voltages referenced to v ss (gnd) 2. zz pin has an internal pull-up, and input leakage is higher.

1. i dd is specified with no output current and increases with faster cycle times. i dd increases with faster cycle times and greater output loading. 2. typical values are measured at 2.5v, 25c, and 10ns cycle time.

1. this parameter is sampled. "#$%&'(&)* +,-). )*/&(&)*# +' 01 2*&(# 3)("# control input capacitance c i t a = 25c; f = 1mhz 5 7 pf 1 input/output capacitance (dq) c o t a = 25c; f = 1mhz 6 8 pf 1 address capacitance c a t a = 25c; f = 1mhz 5 7 pf 1 clock capacitance c ck t a = 25c; f = 1mhz 3 5 pf 1 4! 4 566 577 "#$%&'(&)* +,-). )*/&(&)*# +' 89 89 89 89 2*&(# 3)("# power supply i dd device selected; all inputs v il or v ih ; cycle 900 800 690 580 ma 1, 2 current: operating time = t cyc min; v dd = max; output open power supply i sb 2 device deselected; v dd = max; all inputs 30 60 60 60 60 ma 2 current: standby v ss + 0.2 or vdd - 0.2; all inputs static; clk frequency = 0; zz vil power supply i sb 3 device selected; all inputs v il or v ih ; cycle 20 40 40 40 40 ma 2 current: current time = t cyc min; v dd = max; output open; zz v dd - 0.2v clock running i sb 4 device deselected; v dd = max; all inputs 150 140 130 100 ma 2 standby current v ss + 0.2 or v dd - 0.2; cycle time = t cyc min; zz v il

white electronic designs !" " !!" " !" " #$#%&%$ '( #) '( #) '( #) '( #) '( #) '( #) ('&* clock time t cyc 4.0 4.4 5.0 6.0 6.7 7.5 ns clock access time t cd -- 2.6 -- 2.8 -- 3.0 -- 3.5 -- 3.8 -- 4.2 ns output enable to data valid t oe -- 2.6 -- 2.8 -- 3.0 -- 3.5 -- 3.8 -- 4.2 ns clock high to output low-z t lzc 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns output hold from clock high t oh 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns output enable low to output low-z t lzoe 0.0 -- 0.0 -- 0.0 -- 0.0 -- 0.0 -- 0.0 -- ns output enable high to output high-z t hzoe -- 2.6 -- 2.8 -- 3.0 -- 3.0 -- 3.0 -- 3.5 ns clock high to output high-z t hzc -- 2.6 -- 2.8 -- 3.0 -- 3.0 -- 3.0 -- 3.5 ns clock high pulse width t ch 1.7 -- 2.0 -- 2.0 -- 2.2 -- 2.2 -- 2.2 -- ns clock low pulse width t cl 1.7 -- 2.0 -- 2.0 -- 2.2 -- 2.2 -- 2.2 -- ns address setup to clock high t as 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns cke setup to clock high t ces 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns data setup to clock high t ds 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns write setup to clock high t ws 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns address advance to clock high t advs 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns chip select setup to clock high t css 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns address hold to clock high t ah 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns cke hold to clock high t ceh 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns data hold to clock high t dh 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns write hold to clock high t wh 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns address advance to clock high t advh 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns chip select hold to clock high t csh 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns zz high to power down t pds 2 -- 2 -- 2 -- 2 -- 2 -- 2 -- cycle zz low to power up t pus 2 -- 2 -- 2 -- 2 -- 2 -- 2 -- cycle

( ( (
( dout zo=50 rl=50 vl=1.25v 30pf* dout 1538 5pf* +2.5v 1667

4:!;!<

!4:!;!<
0%0,"("% 0.=" input pulse level 0 to 2.5v input rise and fall time (measured at 20% to 80%) 1.0v/ns input and output timing reference levels 1.25v output load see output load (a) 1. all address inputs must meet the specified setup and hold times for all rising clock (clk) edges when adv is sampled low and cex is sampled valid. all other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. chip enable must be valid at each rising edge of clk (when adv is low) to remain enabled. 3. a write cycle is defined by we low having been registered into the device at adv low. a read cycle is defined by we high with adv low. both cases must meet setup and hold times.

"
()*
white electronic designs snooze mode is a low-current, ?power-down? mode in which the device is deselected and current is reduced to i sb 2 z . the duration of snooze mode is dictated by the length of time z is in a high state. after the device enters snooze mode, all inputs except zz and clk are ignored. zz is an asynchronous, active high input that causes the device to enter snooze mode. when zz becomes a logic high, i sb 2 z is guaranteed after the setup time tzz is met. any read or write operation pending when the device enters snooze mode is not guaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pending opera- tions are completed. "#$%&'(&)* )*/&(&)*# +,-). &* 01 2*&(# 3)("# current during snooze mode zz vih i sb 2 z 10 ma zz active to input ignored t zz 2(t kc )ns 1 zz inactive to input sampled t rzz 2(t kc )ns1 zz active to snooze current t zzi 2(t kc )ns 1 zz inactive to exit snooze current t rzzi ns 1 zz i supply clock a ll inputs (except zz) output (q) t zz t zzi t rzz t rzzi high-z deselect or read only i isb2z don't care

white electronic designs clock ck e address w rite adv oe data ou t t ch t cl t ces t ce h t as t ah a1 a2 a 3 t ws t wh t css t csh t oe t hz oe t lzoe t cd t o h t hzc q3-4 q3-3 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 q1-1 don t care undefined t cyc t advs t a dvh cex notes: write = l means we = l, and bwx = l cex refers to the combination of ce1, ce2 and ce2.

"
()*
white electronic designs clock address write adv data i n t ch t cl a2 a3 d2-1 d1-1 d2-2 d2-3 d2-4 d3-1 d3-2 d3-3 oe data ou t t ds t dh don t care undefined t cyc ck e a1 d3 -4 t ces t ceh q0-4 t hzoe q0-3 cex notes: write = l means we = l, and bwx = l cex refers to the combination of ce1, ce2 and ce2.

white electronic designs cloc a ddress wri te a dv oe data i n t ch t cl t ds t dh data ou t a2 a4 a5 d 2 t oe t lzoe q1 don t care undefined t cyc ck e t ces t ceh a1 a3 a7 a6 q3 q4 q7 q6 d5 a9 a8 cex k notes: write = l means we = l, and bwx = l cex refers to the combination of ce1, ce2 and ce2.

"
()*
white electronic designs clock a ddress writ e adv oe data in t ch t cl data ou t a1 a2 a3 a4 a 5 t ces t ceh don t care undefined t cyc ck e t ds t dh d2 q4 q1 t cd t lzc t hzc q3 a6 cex notes: write = l means we = l, and bwx = l cex refers to the combination of ce1, ce2 and ce2.

white electronic designs clock a ddress writ e adv oe data in t ch t cl data ou t a1 a2 a3 a4 a 5 don t care undefined t cyc ck e d5 q4 t ces t ce h q1 q2 t oe t lz oe d3 t cd t lzc t hz c t dh t ds cex notes: write = l means we = l, and bwx = l cex refers to the combination of ce1, ce2 and ce2.

"
()*
white electronic designs all linear dimensions are in millimeters and parenthetically in inches 2.79 (0.110) max 0.711 (0.028) max 1.27 (0.050) typ 1.27 (0.050) typ a b c d e f g h j k l m n p r t u 17.00 (0.669) typ a1 corner 20.32 (0.800) typ 23.00 (0.905) typ 7.62 (0.300) typ ordering information ),,"%$&0. ",' 0*>" () 0%( 3=,-"% )*?&>=%0(&)* ( .)$@ *# 89 wed2zl361msj26bc 1m x 36 2.6 250 wed2zl361msj28bc 1m x 36 2.8 225 wed2zl361msj30bc 1m x 36 3.0 200 wed2zl361msj35bc 1m x 36 3.5 166 wed2zl361msj38bc 1m x 36 3.8 150 wed2zl361msj42bc 1m x 36 4.2 133 ball attach pad for above bga package is 620 microns in diameter. pad is solder mask defined. */=#(%&0. ",' 0*>" () ! 0%( 3=,-"% )*?&>=%0(&)* ( .)$@ *# 89 wed2zl361msj26bi* 1m x 36 2.6 250 wed2zl361msj28bi 1m x 36 2.8 225 wed2zl361msj30bi 1m x 36 3.0 200 wed2zl361msj35bi 1m x 36 3.5 166 wed2zl361msj38bi 1m x 36 3.8 150 wed2zl361msj42bi 1m x 36 4.2 133 * consult factory for availability

▲Up To Search▲

Price & Availability of WED2ZL361MSJ-BC

	To Download WED2ZL361MSJ-BC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .